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RTL8111D-GR rtl8111dl-gr rtl8111d-vb-gr rtl8111dl-vb-gr rtl8111dl-vb-cg integrated gigabit ethernet controller for pci express applications datasheet (confidential: development partners only) rev. 1.8 21 july 2010 track id: jatr-2265-11 realtek semiconductor corp. no. 2, innovation road ii, hsinchu science park, hsinchu 300, taiwan tel.: +886-3-578-0211. fax: +886-3-577-6047 www.realtek.com
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express ii track id: jatr-2265-11 rev. 1.8 copyright ?2010 realtek semiconductor corp. all rights reserve d. no part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of realtek semiconductor corp. disclaimer realtek provides this document ?as is?, without warranty of any kind. realtek may make improvements and/or changes in this document or in the product de scribed in this document at any time. this document could include technical inaccura cies or typographical errors. trademarks realtek is a trademark of realtek semiconductor cor poration. other names mentioned in this document are trademarks/registered trademarks of their respective owners. license this product is covered by one or more of the following patents: us5,307,459, us5,434,872, us5,732,094, us6,570,884, us 6,115,776, and us6,327,625. using this document this document is intended for the software engin eer?s reference and provides detailed programming information. though every effort has been made to ensure that th is document is current and accurate, more information may have become available subsequent to the production of this guide.
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express iii track id: jatr-2265-11 rev. 1.8 revision history revision release date summary 1.0 2008/05/13 first release. 1.1 2008/07/03 revised section 6.2.6, page 12. added section 9.2, page 37. added section 9.3, page 37. 1.2 2008/07/29 updated licensing information. 1.3 2008/08/08 added deep slumber mode (dsm) power saving to features list on page 2. 1.4 2008/08/29 revised figure 2, page 4 (pin23). 1.5 2009/01/07 switching regulator output revised from 1.2v to 1.05v. revised table 19 crystal requirements, page 27, drive level value. 1.6 2009/03/10 added rtl8111d-vb-gr & rtl8111dl-vb-gr product numbers. added deep slumber mode (dsm) v2 feature on page 2. added section 6.9 deep slumber mode (dsm) v1 & v2, page 19. 1.7 2009/08/14 revised section 5.7 leds, page 7. revised section 6.2.6 customizable led configuration, page 12. revised section 6.5 eepr om interface, page 14. revised section 7 switching regulator, page 20. revised section 9.2 rtl8111dl & rtl8111dl-vb (48-pin lqfp), page 37. revised section 9.3 mechanical dimensions notes (rtl8111dl/rtl8111dl-vb 48-pin), page 37. 1.8 2010/07/21 added rtl8111dl-vb-cg product number.
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express iv track id: jatr-2265-11 rev. 1.8 table of contents 1. general desc ription ............................................................................................................ ..................................1 2. features ....................................................................................................................... ..................................................2 3. system applications............................................................................................................ ...................................2 4. pin assignments ................................................................................................................ .........................................3 4.1. rtl8111d & rtl8111d-vb (64-p in qfn) .............................................................................................................3 4.2. p ackage i dentification ............................................................................................................................... ............3 4.3. rtl8111dl & rtl8111dl-vb (48-p in lqfp).......................................................................................................4 4.4. p ackage i dentification ............................................................................................................................... ............4 5. pin descriptions............................................................................................................... ..........................................5 5.1. p ower m anagement /i solation ..............................................................................................................................5 5.2. pci e xpress i nterface ............................................................................................................................... ..............5 5.3. t ransceiver i nterface ............................................................................................................................... .............6 5.4. c lock ............................................................................................................................... ..........................................6 5.5. r egulator and r eference ............................................................................................................................... .......6 5.6. eeprom ......................................................................................................................... ...........................................7 5.7. led s ............................................................................................................................... ............................................7 5.8. p ower and g round ............................................................................................................................... ...................8 5.9. gpio p ins ............................................................................................................................... ....................................8 5.10. t est p ins ............................................................................................................................... .....................................8 5.11. nc p ins ............................................................................................................................... ........................................8 6. functional description......................................................................................................... ..............................9 6.1. pci e xpress b us i nterface ............................................................................................................................... .......9 6.1.1. pci express transm itter ........................................................................................................ ................................9 6.1.2. pci expres s receiver ........................................................................................................... ..................................9 6.2. led f unctions ............................................................................................................................... ...........................9 6.2.1. link monitor................................................................................................................... ........................................9 6.2.2. rx led ......................................................................................................................... ........................................10 6.2.3. tx led ......................................................................................................................... ........................................10 6.2.4. tx/rx led ...................................................................................................................... ......................................11 6.2.5. link/act led ................................................................................................................... .................................11 6.2.6. customizable led configuration ................................................................................................. .......................12 6.3. phy t ransceiver ............................................................................................................................... ....................13 6.3.1. phy transmitter................................................................................................................ ...................................13 6.3.2. phy r eceiver ................................................................................................................... ....................................13 6.4. n ext p age ............................................................................................................................... .................................14 6.5. eeprom i nterface ............................................................................................................................... .................14 6.6. p ower m anagement ............................................................................................................................... ................15 6.7. v ital p roduct d ata (vpd).......................................................................................................................... .........17 6.8. r eceive -s ide s caling (rss) .......................................................................................................................... ........18 6.8.1. receive-side scaling (rss) initia lization ...................................................................................... .......................18 6.8.2. rss operation .................................................................................................................. ....................................19 6.9. d eep s lumber m ode (dsm) v1 & v2....................................................................................................................19 7. switching regulator............................................................................................................ ..............................20 7.1. i nductor and c apacitor p arts l ist ....................................................................................................................20 7.2. m easurement c riteria ............................................................................................................................... ...........21 7.3. e fficiency m easurement ............................................................................................................................... .......25 7.4. p ower s equence ............................................................................................................................... ......................26
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express v track id: jatr-2265-11 rev. 1.8 8. characteristics................................................................................................................ ......................................27 8.1. a bsolute m aximum r atings ............................................................................................................................... .27 8.2. r ecommended o perating c onditions .................................................................................................................27 8.3. c rystal r equirements ............................................................................................................................... ...........27 8.4. o scillator r equirements ............................................................................................................................... .....28 8.5. t hermal c haracteristics ............................................................................................................................... ......28 8.6. dc c haracteristics ............................................................................................................................... ................28 8.7. ac c haracteristics ............................................................................................................................... ................29 8.7.1. serial eeprom in terface timing ................................................................................................. .......................29 8.8. pci e xpress b us p arameters ............................................................................................................................... .30 8.8.1. differential transm itter para meters ............................................................................................ ........................30 8.8.2. differential recei ver parameters ............................................................................................... ..........................31 8.8.3. refclk para meters.............................................................................................................. ..............................31 8.8.4. auxiliary signal ti ming parameters ............................................................................................. .......................35 9. mechanical dimensions.......................................................................................................... ............................36 9.1. rtl8111d & rtl8111d-vb (64-p in qfn) ...........................................................................................................36 9.2. rtl8111dl & rtl8111dl-vb (48-p in lqfp).....................................................................................................37 9.3. m echanical d imensions n otes (rtl8111dl/rtl8111dl-vb 48-p in )............................................................37 10. ordering information ........................................................................................................... ........................38
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express vi track id: jatr-2265-11 rev. 1.8 list of tables t able 1. p ower m anagement /i solation ............................................................................................................................... 5 t able 2. pci e xpress i nterface ............................................................................................................................... ...............5 t able 3. t ransceiver i nterface ............................................................................................................................... .............6 t able 4. c lock ............................................................................................................................... ...........................................6 t able 5. r egulator and r eference ............................................................................................................................... .......6 t able 6. eeprom ......................................................................................................................... ............................................7 t able 7. led s ............................................................................................................................... .............................................7 t able 8. p ower and g round ............................................................................................................................... ....................8 t able 9. gpio p ins ............................................................................................................................... .....................................8 t able 10. t est p ins ............................................................................................................................... .....................................8 t able 11. nc p ins ............................................................................................................................... ........................................8 t able 12. led s elect (io r egister o ffset 18 h ~19 h )..........................................................................................................12 t able 13. c ustomized led s ............................................................................................................................... ....................12 t able 14. eeprom i nterface ............................................................................................................................... .................14 t able 15. i nductor and c apacitor p arts l ist ....................................................................................................................20 t able 16. p ower s equence p arameter ............................................................................................................................... ..26 t able 17. a bsolute m aximum r atings ............................................................................................................................... .27 t able 18. r ecommended o perating c onditions .................................................................................................................27 t able 19. c rystal r equirements ............................................................................................................................... ...........27 t able 20. o scillator r equirements ............................................................................................................................... .....28 t able 21. t hermal c haracteristics ............................................................................................................................... ......28 t able 22. dc c haracteristics ............................................................................................................................... ................28 t able 23. eeprom a ccess t iming p arameters ..................................................................................................................29 t able 24. d ifferential t ransmitter p arameters ..............................................................................................................30 t able 25. d ifferential r eceiver p arameters .....................................................................................................................31 t able 26. refclk p arameters ............................................................................................................................... ..............31 t able 27. a uxiliary s ignal t iming p arameters .................................................................................................................35 t able 28. o rdering i nformation ............................................................................................................................... ...........38
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express vii track id: jatr-2265-11 rev. 1.8 list of figures f igure 1. rtl8111d & rtl8111d-vb (64-p in qfn) p in a ssignments ...............................................................................3 f igure 2. rtl8111dl & rtl8111dl-vb (48-p in lqfp) p in a ssignments ........................................................................4 f igure 3. r x led............................................................................................................................ .........................................10 f igure 4. t x led............................................................................................................................ .........................................10 f igure 5. t x /r x led............................................................................................................................ ...................................11 f igure 6. link/act led ............................................................................................................................ ...........................11 f igure 7. i nput v oltage o vershoot <4v (g ood )...............................................................................................................21 f igure 8. i nput v oltage o vershoot >4v (b ad ) .................................................................................................................21 f igure 9. c eramic 22 f 1210 (x5r) (g ood )..........................................................................................................................22 f igure 10. c eramic 22 f 0805 (y5v) (b ad ) ...........................................................................................................................22 f igure 11. e lectrolytic 100 f (r ipple t oo h igh ) ...............................................................................................................23 f igure 12. 4r7gtsd32 (g ood ) .............................................................................................................................. .................24 f igure 13. 1 h b ead (b ad ) .............................................................................................................................. ........................24 f igure 14. s witching r egulator e fficiency m easurement c heckpoint ........................................................................25 f igure 15. p ower s equence ............................................................................................................................... .....................26 f igure 16. s erial eeprom i nterface t iming ......................................................................................................................29 f igure 17. s ingle -e nded m easurement p oints for a bsolute c ross p oint and s wing .................................................33 f igure 18. s ingle -e nded m easurement p oints for d elta c ross p oint ..........................................................................33 f igure 19. s ingle -e nded m easurement p oints for r ise and f all t ime m atching .......................................................33 f igure 20. d ifferential m easurement p oints for d uty c ycle and p eriod ...................................................................34 f igure 21. d ifferential m easurement p oints for r ise and f all t ime ...........................................................................34 f igure 22. d ifferential m easurement p oints for r ingback ............................................................................................34 f igure 23. r eference c lock s ystem m easurement p oint and l oading .........................................................................35 f igure 24. a uxiliary s ignal t iming ............................................................................................................................... .......35
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 1 track id: jatr-2265-11 rev. 1.8 1. general description the realtek rtl8111d(l)/rtl8111d(l)-vb gigabit ethe rnet controllers combin e a triple-speed ieee 802.3 compliant media access controller (mac) with a triple-speed ethernet transceiver, pci express bus controller, and embedded memory. with state- of-the-art dsp technology and mixed-mode signal technology, the rtl8111d(l)/rtl8111d(l)-vb offers high-speed transmission over cat 5 utp cable or cat 3 utp (10mbps only) cable. functions su ch as crossover detect ion and auto-correction, polarity correction, adaptive equalization, cross-ta lk cancellation, echo cancella tion, timing recovery, and error correction are implemented to provide robust tr ansmission and reception capability at high speeds. the rtl8111d(l)/rtl8111d(l)-vb supports the pci express 1.1 bus interface for host communications with power management, and is compliant with the ieee 802.3u specification for 10/100mbps ethernet and the ieee 802.3ab specification for 1000mbps et hernet. it also supports an auxiliary power auto-detect function, and will auto-c onfigure related bits of the pci power management registers in pci configuration space. the rtl8111d(l)/rtl8111d(l)-vb features embedded one-time-programmable (otp) memory to re place the external eeprom (93c46/93c56/93c66). advanced configuration power management in terface (acpi)?power mana gement for modern operating systems that are capable of operati ng system-directed power management (ospm)?is supported to achieve the most ef ficient power management possibl e. pci msi (message signaled interrupt) and msi-x are also supported. in addition to the acpi feature, remote wake- up (including amd magic packet? and microsoft? wake-up frame) is supported in both acpi and ap m (advanced power management) environments. to support wol from a deep power down state (e.g., d3co ld, i.e., main power is off and only auxiliary exists), the auxiliary power source must be able to provide the needed power for the rtl8111d(l)/rtl8111d(l)-vb. the rtl8111d(l)/rtl8111d(l)-vb is fully compliant with microsoft ? ndis5, ndis6(ipv4, ipv6, tcp, udp) checksum and segmentation task-offloa d (large send and gian t send) features, and supports ieee 802 ip layer 2 prior ity encoding and ieee 802.1q virtua l bridged local area network (vlan). the above features contribute to lowering cpu utilization, especially benefiting performance when in operation on a network server. the rtl8111d(l)/rtl8111d(l)-vb supports receive side scaling (rss) to hash incoming tcp connections and load-balance received data proce ssing across multiple cpus. rss improves the number of transactions per second and number of connec tions per second, for incr eased network throughput. the device also features inter-connect pci express technology. pci express is a high-bandwidth, low pin count, serial, interconnect tec hnology that offers significant improvements in performance over conventional pci and also maintains software compatib ility with existin g pci infrastructure. the device embeds an adaptive equalizer in the pcie phy for eas e of system integration and excellent link quality. the equalizer enables the length of the pcb traces to reach 40 inches. the rtl8111d(l)/rtl8111d(l)-vb is suitable fo r multiple market segments and emerging applications, such as desktop, mobile, workstati on, server, communications platforms, and embedded applications. the rtl8111d(l)/rtl8111d(l)-vb supports the deep slumber mode (dsm) power saving v1/v2 feature. see the separate dsm application notes for details.
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 2 track id: jatr-2265-11 rev. 1.8 2. features ? integrated 10/100/1000 transceiver ? auto-negotiation with next page capability ? supports pci express 1.1 ? supports pair swap/polarity/skew correction ? crossover detection & auto-correction ? wake-on-lan and remote wake-up support ? microsoft ? ndis5, ndis6 checksum offload (ipv4, ipv6, tcp, udp) and segmentation task-offload (large send v1 and large send v2) support ? supports full duplex flow control (ieee 802.3x) ? supports jumbo frame to 9k bytes ? fully compliant with ieee 802.3, ieee 802.3u, ieee 802.3ab ? supports ieee 802.1p layer 2 priority encoding ? supports ieee 802.1q vlan tagging ? embedded otp memory can replace the external eeprom ? serial eeprom ? transmit/receive on-chip buffer support ? supports power down/link down power saving ? built-in switching regulator ? supports pci msi (message signaled interrupt) and msi-x ? supports quad core receive-side scaling (rss) ? embeds an adaptive equalizer in pci express phy (pcb traces to reach 40 inches) ? supports deep slumber mode (dsm) power saving v1/v2 features (v2 for rtl8111d(l)-vb only) ? customized leds ? packages ? 64-pin qfn ?green? package (rtl8111d & rtl8111d-vb) ? 48-pin lqfp ?green? package (rtl8111dl & rtl8111dl-vb) 3. system applications ? pci express gigabit ethernet on moth erboard, notebook, or embedded system
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 3 track id: jatr-2265-11 rev. 1.8 4. pin assignments 4.1. rtl8111d & rtl8111d-vb (64-pin qfn) figure 1. rtl8111d & rtl8111d-vb (64-pin qfn) pin assignments 4.2. package identification ?green? package is indicated by a ?g? in the locati on marked ?t? in figure 1. the version number is shown in the location marked ?v?.
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 4 track id: jatr-2265-11 rev. 1.8 4.3. rtl8111dl & rtl8111dl-vb (48-pin lqfp) figure 2. rtl8111dl & rtl8111dl- vb (48-pin lqfp) pin assignments 4.4. package identification ?green? package is indicated by a ?g? in the locati on marked ?t? in figure 2. the version number is shown in the location marked ?v?.
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 5 track id: jatr-2265-11 rev. 1.8 5. pin descriptions the signal type codes below are used in the following tables: i: input s/t/s: sustained tri-state o: output o/d: open drain t/s: tri-state bi-directiona l input/output pin p: power 5.1. power management/isolation table 1. power management/isolation symbol type pin no (64-pin) pin no (48-pin) description lanwakeb o/d 19 26 power management event: open drain, active low. used to reactivate the pci express sl ot?s main power rails and reference clocks. isolateb i 36 28 isolate pin: active low. used to isolate the rtl8111d(l)/r tl8111d(l)-vb from the pci express bus. the rtl8111d(l)/rtl8111d(l)-vb will not drive its pci express outputs (excluding lanwakeb) and will not sample its pci express input as long as the isolate pin is asserted. 5.2. pci express interface table 2. pci express interface symbol type pin no (64-pin) pin no (48-pin) description refclk_p i 26 17 refclk_n i 27 18 pci express differential reference clock source: 100mhz 300ppm. hsop o 29 20 hson o 30 21 pci express transmit differential pair. hsip i 23 15 hsin i 24 16 pci express receive differential pair. perstb i 20 27 pci express reset signal: active low. when the perstb is asserted at power-on state, the rtl8111d(l)/rtl8111d(l)-vb returns to a pre-defined reset state and is ready for initialization and configura tion after the de-assertion of the perstb. clkreqb o/d 33 25 reference clock request signal. this signal is used by the rtl8111d(l)/rtl8111d(l)-vb to request starting of the pci express reference clock.
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 6 track id: jatr-2265-11 rev. 1.8 5.3. transceiver interface table 3. transceiver interface symbol type pin no (64-pin) pin no (48-pin) description mdip0 io 3 2 mdin0 io 4 3 in mdi mode, this is the first pair in 1000base-t, i.e., the bi_da+/- pair, and is the transmit pair in 10base-t and 100base-tx. in mdi crossover mode, this pair act s as the bi_db+/- pair, and is the receive pair in 10base-t and 100base-tx. mdip1 io 6 5 mdin1 io 7 6 in mdi mode, this is the second pair in 1000base-t, i.e., the bi_db+/- pair, and is the receive pair in 10base-t and 100base-tx. in mdi crossover mode, this pair acts as the bi_da+/- pair, and is the transmit pair in 10base-t and 100base-tx. mdip2 io 9 8 mdin2 io 10 9 in mdi mode, this is the third pair in 1000base-t, i.e., the bi_dc+/- pair. in mdi crossover mode, this pair acts as the bi_dd+/- pair. mdip3 io 12 11 mdin3 io 13 12 in mdi mode, this is the fourth pair in 1000base-t, i.e., the bi_dd+/- pair. in mdi crossover mode, this pa ir acts as the bi_dc+/- pair. 5.4. clock table 4. clock symbol type pin no (64-pin) pin no (48-pin) description cktal1 i 60 41 input of 25mhz clock reference. cktal2 o 61 42 output of 25mhz clock reference. 5.5. regulator and reference table 5. regulator and reference symbol type pin no (64-pin) pin no (48-pin) description srout12 o 1 48 switching regulator 1.05v output. connect to 5h inductor. fb12 i 5 4 feedback pin for switching regulator. ensr i 62 43 3.3v: enable switching regulator. 0v: disable switching regulator. vddsr p 63 44, 45 digital 3.3v power supply for switching regulator. rset i 64 46 reference. external resistor reference. note: see section 7, page 20 for switching regulator layout.
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 7 track id: jatr-2265-11 rev. 1.8 5.6. eeprom table 6. eeprom symbol type pin no (64-pin) pin no (48-pin) description eesk o 48 35 serial data clock. eedi/aux o/i 47 34 eedi: output to serial data input pin of eeprom. aux: input pin to detect if aux. po wer exists or not on initial power-on. this pin should be connected to eeprom. to support wakeup from acpi d3cold or apm power-down, this pin must be pulled high to aux. power via a resistor. if this pin is not pulled high to aux. power, the rtl8111d(l)/rtl8111d(l)-vb assumes that no aux. power exists. eedo i 45 33 input from serial data output pin of eeprom. eecs o 44 32 eecs: eeprom chip select. 5.7. leds table 7. leds symbol type pin no (64-pin) pin no (48-pin) description led0 o 57 38 led1 o 56 35 led2 o 55 34 led3 o 54 33 leds1-0 00 01 10 11 led0 tx/rx tx/rx tx link10/ act led1 link100 link10/ 100/1000 link link100/ act led2 link10 link10/ 100 rx full duplex led3 link1000 link1000 full duplex link1000 /act note 1: during power down mode, the led signals are logic high. note 2: leds1-0?s initial va lue comes from the eeprom. if there is no eeprom, the de fault value of the (leds1, leds0)=(1,1). when implementing dual color leds and eeprom at the same time: pin33, pin34, and pin35 of the rtl8111dl are shared pins. follow the rtl8111dl reference design (version 1.07 or later) to select 2 pins from these 3 sh ared pins for a dual color led circuit. otherwise, the rtl8111dl eeprom may not function.
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 8 track id: jatr-2265-11 rev. 1.8 5.8. power and ground table 8. power and ground symbol type pin no (64-pin) pin no (48-pin) description vdd33 p 16, 37, 46, 53 29, 37 digital 3.3v power supply. dvdd12 p 21, 32, 38, 43, 49, 52 13, 30, 36 digital 1.05v power supply. avdd12 p 8, 11, 14, 58 10, 39 analog 1.05v power supply. evdd12 p 22, 28 19 analog 1.05v power supply. avdd33 p 2, 59 1, 40 analog 3.3v power supply. egnd p 25, 31 22 analog ground. gnd p 65 7, 14, 31, 47 ground (exposed pad). note: refer to the most updated schematic circuit for correct configuration. 5.9. gpio pins table 9. gpio pins symbol type pin no (64-pin) pin no (48-pin) description gpi i 50 - general purpose input pin. gpo o 51 23 general purpose output pin. this pin reflects the link up or link down state. high: link up low: link down 5.10. test pins table 10. test pins symbol type pin no (64-pin) pin no (48-pin) description test - 34, 35, 39, 40, 41, 42 - realtek internal use only. 5.11. nc pins table 11. nc pins symbol type pin no (64-pin) pin no (48-pin) description nc - 15, 17, 18 24 not connected.
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 9 track id: jatr-2265-11 rev. 1.8 6. functional description 6.1. pci express bus interface the rtl8111d(l)/rtl8111d(l)-vb complies with pc i express base specification revision 1.1, and runs at a 2.5ghz signaling rate w ith x1 link width, i.e., one transmit and one receive differential pair. the rtl8111d(l)/rtl8111d(l)-vb supports four types of pci express messages: interrupt messages, error messages, power management messages, and hot -plug messages. to ease pcb layout constraints, pci express lane polarity reversal and link reversal are also supported. 6.1.1. pci express transmitter the rtl8111d(l)/rtl8111d(l)-vb?s pci express block receives digital data from the ethernet interface and performs data scrambling with linear feedback shift register (lfsr) and 8b/10b coding technology into 10-bit c ode groups. data scrambling is used to reduce the possibil ity of electrical resonance on the link, and 8b/10b coding technology is used to benefit embedded clocking, error detection, and dc balance by adding an overhead to th e system through the addition of 2 extra bits. the data code groups are passed through its serializer for packet framing. th e generated 2.5gbps serial data is transmitted onto the pcb trace to its upstr eam device via a differential driver. 6.1.2. pci express receiver the rtl8111d(l)/rtl8111d(l)-vb?s pci express block receives 2.5g bps serial data from its upstream device to generate parallel data. the receiver?s pll circuits are re-synchronized to maintain bit and symbol lock. through 8b/10b decoding technology and data de-scram bling, the original digital data is recovered and passed to the rtl8111d(l)/rtl8111d(l)-vb?s in ternal ethernet mac to be transmitted onto the ethernet media. 6.2. led functions the rtl8111d(l)/rtl8111d(l)-vb supports four led signa ls in four different configurable operation modes. the following sections describe the various led actions. 6.2.1. link monitor the link monitor senses link integrity, su ch as link10, link100, link1000, link10/100/1000, link10/act, link100/act, or link 1000/act. whenever link status is established, the specific link led pin is driven low. once a cable is disconnected, the link led pin is driven high, indicating that no network connection exists.
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 10 track id: jatr-2265-11 rev. 1.8 6.2.2. rx led in 10/100/1000mbps mode, blinking of the rx led indicates that receive activity is occurring. figure 3. rx led 6.2.3. tx led in 10/100/1000mbps mode, blinking of the tx led indicates that transmit activity is occurring. figure 4. tx led
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 11 track id: jatr-2265-11 rev. 1.8 6.2.4. tx/rx led in 10/100/1000mbps mode, blinking of the tx/rx led i ndicates that both transm it and receive activity is occurring. figure 5. tx/rx led 6.2.5. link/act led in 10/100/1000mbps mode, b linking of the link/act led indicates that the rtl8111d(l)/rtl8111d(l)-vb is linked and operating properly. when this led is high for extended periods, it indicates that a link problem exists. figure 6. link/act led
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 12 track id: jatr-2265-11 rev. 1.8 6.2.6. customizable led configuration the rtl8111d(l)/rtl8111d(l)-vb supports customizable led operation modes via io register offset 18h~19h. table 12 describes the different led actions. table 12. led select (io register offset 18h~19h) bit symbol rw description 15:12 ledsel3 rw led select for pinled3 11:8 ledsel2 rw led select for pinled2 7:4 ledsel1 rw led select for pinled1 3:0 ledsel0 rw led select for pinled0 when implementing customized leds: 1. set io register offset 0x55 bit 6 to 1h to enable the customized led function 2. configure io register offset 18h~ 19h to support your own led signals. fo r example, if the value in the io offset 0x18 is 0x8ec1h ( 1000111011000001b), the led actions are: ? led 0: on only in 10m mode, with no blinking during tx/rx ? led 1: on only in 1000m m ode, with tx/rx blinking ? led 2: on only in 100m/1000m mode, with tx/rx blinking ? led 3: on only in full duplex mode table 13. customized leds link act/full speed link 10m link 100m link 1000m - led 0 bit 0 bit 1 bit 2 bit 3 led 1 bit 4 bit 5 bit 6 bit 7 led 2 bit 8 bit 9 bit 10 bit 11 led 3 bit 12 bit 13 bit 14 bit 15 led pin act=0 act=1 link=0 floating led on when in full duplex mode link>0 led on when selected speed is linked led blin ks on selected speed tx/rx note1: act means blinking tx and rx. link indicates link 10m and link 100m. note2: there are two special modes: mode a: led off mode ? set all bits to 0. mode b: tx/rx mode ? set led 0=0, and either led 1, led 2, or led 3 >0. led 0 = blinking on tx/rx. led 1 = follow customized led rule. led 2 = follow customized led rule. led 3= follow customized led rule.
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 13 track id: jatr-2265-11 rev. 1.8 6.3. phy transceiver 6.3.1. phy transmitter based on state-of-the-art dsp technology and mixed-mode signa l processing technology, the rtl8111d(l)/rtl8111d(l)-vb operates at 10/100/ 1000mbps over standard cat.5 utp cable (100/1000mbps), and cat.3 utp cable (10mbps). gmii (1000mbps) mode the rtl8111d/rtl8111d-vb?s pcs layer receives data bytes from the mac through the gmii interface and performs the generation of continu ous code-groups through 4d-pam5 coding technology. these code groups are passed through a waveform-s haping filter to minimize emi effects, and are transmitted onto the 4-pair cat5 cable at 125mbaud/s through a d/a converter. mii (100mbps) mode the transmitted 4-bit nibbles (txd[3:0]) from the ma c, clocked at 25mhz (txc), are converted into 5b symbol code through 4b/5b coding technology, then through scrambling and serializing, are converted to 125mhz nrz and nrzi signals. after that, the nrzi signals are passed to the mlt3 encoder, then to the d/a converter and transmitted onto the media. mii (10mbps) mode the transmitted 4-bit nibbles (txd[3:0]) from the mac, clocked at 2.5mhz (txc), are serialized into 10mbps serial data. the 10mbps serial data is convert ed into a manchester-encoded data stream and is transmitted onto the media by the d/a converter. 6.3.2. phy receiver gmii (1000mbps) mode input signals from the media pass through the sophi sticated on-chip hybrid ci rcuit to separate the transmitted signal from the input signal for effectiv e reduction of near-end ec ho. afterwards, the received signal is processed with state-of -the-art technology, e.g., adaptive e qualization, blw (baseline wander) correction, cross-talk cancellati on, echo cancellation, timing recover y, error correction, and 4d-pam5 decoding. then, the 8-bit-wide data is recovered and is sent to the gmii interface at a clock speed of 125mhz. the rx mac retrieves the packet data from the receive mii/gmii interf ace and sends it to the rx buffer manager. mii (100mbps) mode the mlt3 signal is processed with an adc, equalizer, blw (baseline wander) correction, timing recovery, mlt3 and nrzi decoder, descrambler, 4b /5b decoder, and is then presented to the mii interface in 4-bit-wide nibbles at a clock speed of 25mhz. mii (10mbps) mode the received differential signal is converted into a manchester-encoded st ream first. next, the stream is processed with a manchester decoder and is de-seria lized into 4-bit-wide nibbles. the 4-bit nibbles are presented to the mii interface at a clock speed of 2.5mhz.
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 14 track id: jatr-2265-11 rev. 1.8 6.4. next page if 1000base-t mode is advertised, three additional next pages are automatica lly exchanged between the two link partners. users can set phy reg4.15 to 1 to manually exchange extra next pages via reg7 and reg8 as defined in ieee 802.3ab. 6.5. eeprom interface the rtl8111d(l)/rtl8111d(l)-vb requires the at tachment of an external eeprom. the 93c46/93c56/93c66 is a 1k-bit/2k-bit eeprom. th e eeprom interface permits the rtl8111d(l)/ rtl8111d(l)-vb to read from, and write data to, an external serial eeprom device. note: the rtl8111dl/rtl8111dl-vb only supports 93c46 eeprom. values in the internal efuse memory or external eeprom allow default fields in pci configuration space and i/o space to be overridden following a power-on or software eeprom auto-load command. the rtl8111d(l)/rtl8111d(l)-vb will auto-load va lues from the efuse or eeprom. if the eeprom is not present and efuse auto-loa d is bypassed, the r tl8111d(l)/rtl8111d(l)-vb initialization uses default values for the appropriate configuration and operatio nal registers. software can read and write to the eeprom using bit-bang accesses via the 9346cr register, or using pci vpd (vital product data). the interface consists of eesk , eecs, eedo, and eedi. the correct eeprom (i.e., 93c46/93c56/93c66) must be used in order to ensure proper lan function. table 14. eeprom interface eeprom description eecs 93c46/93c56/93c66 chip select. eesk eeprom serial data clock. eedi/aux input data bus/input pin to detect whether aux. power exists on initial power-on. this pin should be connected to eeprom. to support wakeup from acpi d3cold or apm power-down, this pin must be pulled high to aux. power via a resistor. if this pin is not pulled high to aux. power, the rtl8111d(l)/rtl8111d(l)-vb assumes that no aux. power exists. eedo output data bus.
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 15 track id: jatr-2265-11 rev. 1.8 6.6. power management the rtl8111d(l)/rtl8111d(l)-vb complies with acpi (rev 1.0, 1.0b, 2.0), pci power management (rev 1.1), pci express active state power manage ment (aspm), and network device class power management reference specification (v1.0a), such as to support an operating system-directed power management (ospm) environment. the rtl8111d(l)/rtl8111d(l)-vb can monitor the ne twork for a wakeup frame, a magic packet, and notify the system via a pci express powe r management event (pme) message, beacon, or lanwakeb pin when such a packet or event occurs. th en the system can be restored to a normal state to process incoming jobs. when the rtl8111d(l)/rtl8111d(l)-vb is in power down mode (d1 ~ d3): ? the rx state machine is stopped. the rtl8111d( l)/rtl8111d(l)-vb monitors the network for wakeup events such as a magic packet and wakeup frame in order to wake up the system. when in power down mode, the rtl8111d(l)/rtl8111d(l)-vb will not reflect the status of any incoming packets in the isr register and will not rece ive any packets into the rx on-chip buffer. ? the on-chip buffer status and packets that have already been received into the rx on-chip buffer before entering power down mode are he ld by the rtl8111d(l)/rtl8111d(l)-vb. ? transmission is stopped. pci express transactio ns are stopped. the tx on-chip buffer is held. ? after being restored to d0 st ate, the rtl8111d(l)/rtl8111d(l)-vb transmits data that was not moved into the tx on-chip buffer during power down mode. packets that were not transmitted completely last time are re-transmitted. the d3 cold _support_pme bit (bit15, pmc regist er) and the aux_i_b2:0 bits (b it8:6, pmc register) in pci configuration space depend on the existence of aux power . if aux. power is absent, the above 4 bits are all 0 in binary. example: if eeprom d3c_support_pme = 1: ? if aux. power exists, then pmc in pci c onfig space is the same as eeprom pmc (if eeprom pmc = c3 ff, then pci pmc = c3 ff) ? if aux. power is absent, then pmc in pci conf ig space is the same as eeprom pmc except the above 4 bits are all 0?s (if eeprom pmc = c3 ff, then pci pmc = 03 7e) in the above case, if wakeup support is desired when main power is off, it is suggested that the eeprom pmc be set to c3 ff (realtek eeprom default value).
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 16 track id: jatr-2265-11 rev. 1.8 if eeprom d3c_support_pme = 0: ? if aux. power exists, then pmc in pci c onfig space is the same as eeprom pmc (if eeprom pmc = c3 7f, then pci pmc = c3 7f) ? if aux. power is absent, then pmc in pci conf ig space is the same as eeprom pmc except the above 4 bits are all 0?s (if eeprom pmc = c3 7f, then pci pmc = 03 7e) in the above case, if wakeup support is not desired wh en main power is off, it is suggested that the eeprom pmc be set to 03 7e. magic packet wakeup occurs only when the following conditions are met: ? the destination address of the receiv ed magic packet is acceptable to the rtl8111d(l)/rtl8111d(l)-vb, e.g., a broadcast, multicast, or unicast packet addressed to the current rtl8111d(l)/rtl8111d(l)-vb. ? the received magic packet does not contain a crc error. ? the magic bit (config3#5) is set to 1, the pmen bit (config1#0) is set to 1, and the corresponding wake-up method (message, beacon, or lanwakeb) can be asserted in the current power state. ? the magic packet pattern matches, i.e., 6 * ffh + misc (can be none) + 16 * did (destination id) in any part of a valid ethernet packet. a wakeup frame event occurs only wh en the following conditions are met: ? the destination address of the receiv ed wakeup frame is acceptable to the rtl8111d(l)/rtl8111d(l)-vb, e.g., a broadcast, multicast, or unicast address to the current rtl8111d(l)/rtl8111d(l)-vb. ? the received wakeup frame does not contain a crc error. ? the pmen bit (config1#0) is set to 1. ? the 16-bit crc a of the received wakeup frame matches the 16-bit crc of the sample wakeup frame pattern given by the local machine?s os. or, the rtl8111d(l)/rtl8111d(l)-vb is configured to allow direct packet wakeup, e.g., a broadcast, multicast, or unicast network packet. note: 16-bit crc: the rtl8111d(l)/rtl8111d(l)-vb supports eight long wakeup frames (covering 128 mask bytes from offset 0 to 127 of any incoming network packet).
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 17 track id: jatr-2265-11 rev. 1.8 the corresponding wake-up method (message or la nwakeb) is asserted only when the following conditions are met: ? the pmen bit (bit0, config1) is set to 1. ? the pme_en bit (bit8, pmcsr) in pc i configuration space is set to 1. ? the rtl8111d(l)/rtl8111d(l)-vb may assert th e corresponding wake-up method (message or lanwakeb) in the current power state or in isolation state, depending on the pme_support (bit15-11) setting of the pmc regist er in pci configuration space. ? a magic packet, linkup, or wakeup frame has been received. ? writing a 1 to the pme_status (bit15) of the pmcsr register in the pci configuration space clears this bit and causes the rtl8111d(l)/rtl8111d(l)-v b to stop asserting the corresponding wake-up method (message or lanwakeb) (if enabled). when the rtl8111d(l)/rtl8111d(l)-vb is in pow er down mode, e.g., d1 -d3, the io and mem accesses to the rtl8111d(l)/rtl8111d (l)-vb are disabled. after a pe rstb assertion, the device?s power state is restored to d0 automati cally if the original power state was d3 cold . there is almost no hardware delay at the device?s pow er state transition. when in acpi mode, the device does not support pme (power management enable) from d0 (this is the realtek default setting of the pmc register auto-loaded from eeprom). the setting may be changed from the eeprom, if required. 6.7. vital product data (vpd) bit 31 of the vital product data (vpd) capability structure in the rtl8111d/rtl8111d-vb?s pci configuration space is used to issue vpd read/write commands and is also a flag used to indicate whether the transfer of data be tween the vpd data register and the 93c46/93c56/93c66 has completed or not. write vpd register: (write data to the 93c46/93c56/93c66) set the flag bit to 1 at the same time the vpd addr ess is written to write vpd data to eeprom. when the flag bit is reset to 0 by the rtl8111d/rtl8111d-vb, the vpd data (4 bytes per vpd access) has been transferred from the vpd data register to eeprom. read vpd register: (read data from the 93c46/93c56/93c66) reset the flag bit to 0 at the same time the vpd addr ess is written to retrieve vpd data from eeprom. when the flag bit is set to 1 by the rtl8111d/rtl8111d-vb, the vpd data (4 bytes per vpd access) has been transferred from eepro m to the vpd data register. note1: refer to the pci 2.3 specifi cations for further information. note2: the vpd address must be a dword-aligned address as defined in the pci 2.3 specifications. vpd data is always consecutive 4-byte dat a starting from the vpd address specified. note3: realtek reserves offset 60h to 7fh in eeprom mainly for vpd data to be stored. note4: the vpd function of the rtl8111d(l)/rtl8111d( l)-vb is designed to be able to access the full range of the 93c46/93c56/93c66 eeprom.
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 18 track id: jatr-2265-11 rev. 1.8 6.8. receive-side scaling (rss) the rtl8111d(l)/rtl8111d(l)-vb is compliant with the network driver in terface specification (ndis) 6.0 receive-side scaling (rss) technology for the microsof t windows family of operating systems. rss allows packet receive-processing from a network adapter to be balanced across the number of available computer processors, increasing performance on multi cpu platforms. 6.8.1. receive-side scaling (rss) initialization during rss initialization, the windows operating system will inform the rtl8111d(l)/rtl8111d(l)-vb that it should store the following parame ters: hash function, hash type, hash bits, indirection table, base cpunumber, and the secret hash key. hash function the default hash function is the toeplitz hash function. hash type the hash types indicate which field of the packet n eeds to be hashed to get the hash result. there are several combinations of these fields, mainl y, tcp/ipv4, ipv4, tcp/ipv6, ipv6, and ipv6 extension headers. ? tcp/ipv4 requires hash calculations over the ipv4 source address, the ipv4 destination address, the source tcp port and the destination tcp port. ? ipv4 requires hash calculations over the ipv4 sour ce address and the ipv4 de stination address. ? tcp/ipv6 requires hash calculations over the ipv6 source address, the ipv6 destination address, the source tcp port and the destination tcp port. ? ipv6 requires hash calculations over the ipv6 s ource address and the ip v6 destination address (note: the rtl8111d(l)/rtl8111d(l)-vb does not s upport the ipv6 extension header hash type in rss). hash bits hash bits are used to index the ha sh result into the indirection table indirection table the indirection table stores values that are added to the basecpunumber to enable rss interrupts to be restricted from some cpus. the os will update the indirection table to rebalance the load. basecpunumber the lowest number cpu to use for rss. basecpunumber is added to the result of the indirection table lookup. secret hash key the key used in the toeplitz function. for differe nt hash types, the key size is different.
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 19 track id: jatr-2265-11 rev. 1.8 6.8.2. rss operation after the parameters are set, the rtl8111d(l)/r tl8111d(l)-vb will start ha sh calculation on each incoming packet and forward each packet to its correct queue according to the hash result. if the incoming packet is not in the hash type, it will be forwar ded to the primary queue. the hash result plus the basecpunumber will be indexed into the indirec tion table to get the correct cpu number. the rtl8111d(l)/rtl8111d(l)-vb uses three methods to in form the system of incoming packets: inline interrupt, msi, and msix. periodica lly the os will update the indirect ion table to rebalance the load across the cpus. 6.9. deep slumber mode (dsm) v1 & v2 the rtl8111d(l)/rtl8111d(l)-vb supports link down power saving mode via communication with the bios and external circuitry. no te that dsmv2 is a simplified im plementation of dsmv1, and is only supported in the rtl8111d(l)-vb. refer to the separate dsm applicat ion note for details.
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 20 track id: jatr-2265-11 rev. 1.8 7. switching regulator the rtl8111d(l)/rtl8111d(l)-vb incorporates a stat e-of-the-art switching re gulator that requires a well-designed pcb layout in order to achieve good pow er efficiency and lower the output voltage ripple and input overshoot. note that th e switching regulator 1.05v output pi n (srout12) must be connected only to dvdd12 and avdd12 (do not provide this power source to other devices). note: refer to the separate layout guide for details. 7.1. inductor and capacitor parts list table 15. inductor and capacitor parts list inductor type inductance esr at 1mhz (m ? ) max idc (ma) output ripple (mv) 4r7gtsd32 4.7h 712 1100 12.6 6r8gtsd32 6.8h 784 900 12 6r8gtsd53 6.8h 737 1510 10.4 note 1: the esr is equivalent to rdc or dcr. lower esr inductor values will promote a higher efficiency switching regulator. note 2: the power inductor used by the switching regulator must be able to withstand 600ma of current. note 3: typically, if the power inductor?s esr at 1mhz is below 0.8 , the switching regulator efficiency will be above 75%. however the actual switching regulator efficiency should be measured according to the method described in section 7.3 efficiency measurement, page 25. capacitor type capacitance esr at 1mhz (m ? ) output ripple (mv) 22f 1210 tdk 21.5f 33.53 9.6 22f 1210 x5r 22.15f 34.11 10.4 note: capacitors (c18 & c82) are suggested to be ceramic due to their low esr value. lower esr values will yield lower output voltage ripple.
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 21 track id: jatr-2265-11 rev. 1.8 7.2. measurement criteria in order for the switching regulator to operate properly, the input and ou tput voltage meas urement criteria must be met. from the input side, the voltage ov ershoot cannot exceed 4v; otherwise the chip may be damaged. note that the voltage signal must be measured directly at th e vddsr pin, not at the capacitor. in order to reduce the input voltage overshoot, the c82 and c83 must be placed close to the vddsr pin. the following figures show what a good i nput voltage and a bad one look like. figure 7. input voltage overshoot <4v (good) figure 8. input voltage overshoot >4v (bad)
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 22 track id: jatr-2265-11 rev. 1.8 from the output side measured at the srout12 pin, the voltage rippl e must be within 100mv. choosing different types and values of output capacitor (c18, c 19) and power inductor (l20) will seriously affect the efficiency and output voltage ripple of switching regulators. the following figures show the effects of different types of capacitors on the switching regulator?s output voltage. the blue square wave signal (top row) is measured at the output the srout12 pin before the power inductor (l20). the yellow signal (s econd row) is measured after the power inductor (l20), and shows there is a voltage ripple. the green signal (lower ro w) is the current. data in the following figures was measured at gigabit speed. figure 9. ceramic 22f 1210 (x5r) (good) figure 10. ceramic 22f 0805 (y5v) (bad)
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 23 track id: jatr-2265-11 rev. 1.8 a ceramic 22f (x5r) will have a lower voltage ripple compared to the electrolytic 100f. the key to choosing a proper output capacitor is to choose the lowest esr to reduce the output voltage ripple. choosing a ceramic 22f 0805 (y5v) in this case will caus e malfunction of the switching regulator. placing several electrolytic capacitors in parall el will help lower the output voltage ripple. figure 11. electrolytic 100f (ripple too high)
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 24 track id: jatr-2265-11 rev. 1.8 the following figures show how different inductor s affect the srout12 pin output waveform. the typical waveform should look like figure 12, which has a square waveform with a dip at the falling edge and the rising edge. if the inducto r is not carefully chos en, the waveform may look like figure 13, where the waveform looks like a distorted square. this w ill cause insufficient current supply and will undermine the stability of the system at giga bit speed. data in the following figur es was measured at gigabit speed. figure 12. 4r7gtsd32 (good) figure 13. 1h bead (bad)
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 25 track id: jatr-2265-11 rev. 1.8 7.3. efficiency measurement the efficiency of the switching regula tor is designed to be above 75% in gigabit traffic m ode. it is very important to choose a suitable inductor before gerber certification, as the induc tor esr value will affect the efficiency of the switching regulator. an induc tor with a lower esr value will result in a higher efficiency switching regulator. the efficiency of the switching regulator is easily measured using the following method. figure 14 shows two checkpoints, checkpoint a (cp_a) and check point b (cp_b). the switching regulator input current (ic pa) should be measured at cp_a, a nd the switching regula tor output current (icpb) should be measured at cp_b. to determine efficiency, apply the following formula: efficiency = vcpb*icpb / vcpa*icpa where vcpb is 1.05v; vcpa is 3.3v. the measurements should be performed in gigabit traffic mode. for example: the inductor used in the ev aluation board is a gotrend gtsd32-4r7m: ? the esr value @ 1mhz is approximately 0.712ohm ? the measured icpa is 101ma at cp_a ? the measured icpb is 263ma at cp_b these values are measured in gigabit traffic mo de, so the efficiency of the gotrend gtsd32-4r7m can be calculated as follows: efficiency = (1.05v*263ma) / (3.3v*101ma) = 0.823 = 82.3%. we strongly recommend that when choosing an inducto r for the switching regulat or, the efficiency should be measured, and that the inductor should yield an e fficiency rating higher than 75%. if the efficiency does not meet this requirement, ther e may be risk to the switching re gulator reliability in the long run. figure 14. switching regulator efficiency measurement checkpoint cp_b cp_a
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 26 track id: jatr-2265-11 rev. 1.8 7.4. power sequence figure 15. power sequence table 16. power sequence parameter symbol description min typical max units rt1 3.3v rise time 1 - 100 ms rt2 3.3v fall time 200 - - ms note 1: the rtl8111d(l)/rtl8111d(l)-vb does not support fast 3.3v rising. the 3.3v rise time must be controlled over 1ms. if the rise time is too short it will induce a peak vo ltage in pin63, which may ca use permanent damage to the switching regulator. note 2: if there is any action that involves consecutive on/off toggling of the switching-regulator source (3.3v), the design must makes sure the off state of both the switching-regulator source (3.3v) and output (1.05v) reach 0v, and the time period between the consecutive on/off toggling action must be longer than 200ms.
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 27 track id: jatr-2265-11 rev. 1.8 8. characteristics 8.1. absolute maximum ratings warning: absolute maximum ratings are limits beyond which permanent damage may be caused to the device, or device reliability will be affected. all voltages are specified reference to gnd unless otherwise specified. table 17. absolute maximum ratings symbol description minimum maximum unit vdd33, avdd33 supply voltage 3.3v -0.3 +0.30 v avdd12, dvdd12 supply voltage 1.05v -0.3 +0.12 v evdd12 supply voltage 1.05v -0.3 +0.12 v dcinput input voltage -0.3 corresponding supply voltage + 0.5 v dcoutput output voltage -0.3 corresponding supply voltage + 0.5 v n/a storage temperature -55 +125 c note: refer to the most updated schematic circuit for correct configuration. 8.2. recommended operating conditions table 18. recommended operating conditions description pins minimum typical maximum unit vdd33, avdd33 2.97 3.3 3.63 v avdd12, dvdd12 1.0 1.05 1.09 v supply voltage vdd evdd12 1.0 1.05 1.09 v ambient operating temperature t a - 0 - 70 c maximum junction temperature - - - 125 c note: refer to the most updated schematic circuit for correct configuration. 8.3. crystal requirements table 19. crystal requirements symbol description/condition minimum typical maximum unit f ref parallel resonant crystal reference frequency, fundamental mode, at-cut type. - 25 - mhz f ref stability parallel resonant crystal frequency stability, fundamental mode, at-cut type. t a = 0 c ~ +70 c. -30 - +30 ppm f ref tolerance parallel resonant crystal frequency tolerance, fundamental mode, at-cut type. t a = 25 c. -50 - +50 ppm f ref duty cycle reference clock input duty cycle. 40 - 60 % esr equivalent series resistance. - - 30 ? dl drive level. - - 0.3 mw note: the clk source can come from other places in the system, but it must accord with the parameters above.
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 28 track id: jatr-2265-11 rev. 1.8 8.4. oscillator requirements table 20. oscillator requirements parameter condition minimum typical maximum unit frequency - - 25 - mhz frequency stability t a = 0 c ~ +70 c -30 - +30 ppm frequency tolerance t a = 25 c -50 - +50 ppm duty cycle - 40 - 60 % jitter - - - 50 ps vp-p - 3.15 3.3 3.45 v rise time - - - 10 ns fall time - - - 10 ns operation temp range - 0 - 70 c note: the clk source can come from other places in the system, but it must accord with the parameters above. 8.5. thermal characteristics table 21. thermal characteristics parameter minimum maximum units storage temperature -55 +125 c ambient operating temperature 0 70 c 8.6. dc characteristics table 22. dc characteristics symbol parameter conditions minimum typical maximum units vdd33, avdd33 3.3v supply voltage - 2.97 3.3 3.63 v dvdd12, avdd12 1.05v supply voltage - 1.0 1.05 1.09 v evdd12 1.05v supply voltage - 1.0 1.05 1.09 v v oh minimum high level output voltage i oh = -4ma 0.9*vdd33 - vdd33 v v ol maximum low level output voltage i ol = 4ma 0 - 0.1*vdd33 v v ih minimum high level input voltage - 2.0 - - v v il maximum low level input voltage - - - 0.8 v i in input current vin = vdd33 or gnd 0 - 0.5 a icc33 average operating supply current from 3.3v at 1gbps with heavy network traffic - 66 - ma icc12 average operating supply current from 1.05v at 1gbps with heavy network traffic - 272 - ma note: refer to the most updated schematic circuit for correct configuration.
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 29 track id: jatr-2265-11 rev. 1.8 8.7. ac characteristics 8.7.1. serial eeprom interface timing 93c46(64*16)/93c56(128*16)/93c66(256*16) eesk eecs eedi eedo 11 0 an a2 a0 a1 dn d1 d0 eesk (read) (write) (read) (write) 0 tcs eesk eecs eedi eedo 11 0 an a0 ... dn tcs ... busy ready high impedance high impedance twp eecs eedi eedo eedo (read) (program) status valid tsk tskh tskl tcss tdis tdih tdos tdoh tcsh tsv d0 figure 16. serial eeprom interface timing table 23. eeprom access timing parameters symbol parameter eeprom type min. max. unit tcs minimum cs low time 9346/9356/9366 1000 - ns twp write cycle time 9346/9356/9366 - 10 ms tsk sk clock cycle time 9346/9356/9366 4 - s tskh sk high time 9346/9356/9366 1000 - ns tskl sk low time 9346/9356/9366 1000 - ns tcss cs setup time 9346/9356/9366 200 - ns tcsh cs hold time 9346/9356/9366 0 - ns tdis di setup time 9346/9356/9366 400 - ns tdih di hold time 9346/9356/9366 400 - ns tdos do setup time 9346/9356/9366 2000 - ns tdoh do hold time 9346/9356/9366 - 2000 ns tsv cs to status valid 9346/9356/9366 - 1000 ns
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 30 track id: jatr-2265-11 rev. 1.8 8.8. pci express bus parameters 8.8.1. differential transmitter parameters table 24. differential transmitter parameters symbol parameter min typical max units ui unit interval 399.88 400 400.12 ps v tx-diffp-p differential peak to peak output voltage 0.800 - 1.05 v v tx-de-ratio de-emphasized differential output vo ltage (ratio) -3.0 -3.5 -4.0 db t tx-eye minimum tx eye width 0.75 - - ui t tx-eye-median- to-max-jitter maximum time between the jitter median and maximum deviation from the median - - 0.125 ui t tx-rise , t tx-fall d+/d- tx output rise/fall time 0.125 - - ui v tx-cm-acp rms ac peak common mode output voltage - - 20 mv v tx-cm-dcactive- idledelta absolute delta of dc common mode voltage during l0 and electrical idle 0 - 100 mv v tx-cm-dcline- delta absolute delta of dc common mode voltage between d+ and d- 0 - 25 mv v tx-idle-diffp electrical idle differential peak output voltage 0 - 20 mv v tx-rcv-detect the amount of voltage change allowed during receiver detection - - 600 mv v tx-dc-cm the tx dc common mode voltage 0 - 3.6 v i tx-short tx short circuit current limit - - 90 ma t tx-idle-min minimum time spent in electrical idle 50 - - ui t tx-idle- setto-idle maximum time to transition to a valid electrical idle after sending an electrical idle ordered set - - 20 ui t tx-idle-toto- diff-data maximum time to transition to valid tx specifications after leaving an electrical idle condition - - 20 ui rl tx-diff differential return loss 10 - - db rl tx-cm common mode return loss 6 - - db z tx-diff-dc dc differential tx impedance 80 100 120 ? l tx-skew lane-to-lane output skew - - 500+2*ui ps c tx ac coupling capacitor 75 - 200 nf t crosslink crosslink random timeout 0 - 1 ms note1: refer to pci express base specification, rev.1.1, fo r correct measurement environment setting of each parameter. note2: the data rate can be modulated with an ssc (spread spectrum clock) from +0 to -0.5% of the nominal data rate frequency, at a modulation rate in th e range not exceeding 30khz ? 33khz. th e 300ppm requiremen t still holds, which requires the two communicating ports be modulated such that they never exceed a to tal of 600ppm difference.
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 31 track id: jatr-2265-11 rev. 1.8 8.8.2. differential receiver parameters table 25. differential receiver parameters symbol parameter min. typical max. units ui unit interval 399.88 400 400.12 ps v rx-diffp-p differential input peak to peak voltage 0.175 - 1.05 v t rx-eye minimum receiver eye width 0.4 - - ui t rx-eye-median-to- max-jitter maximum time between the jitter median and maximum deviation from the median - - 0.3 ui v rx-cm-acp ac peak common mode input voltage - - 150 mv rl rx-diff differential return loss 10 - - db rl rx-cm common mode return loss 6 - - db z rx-diff-dc dc differential input impedance 80 100 120 ? z rx--dc dc input impedance 40 50 60 ? z rx-high-imp-dc powered down dc input impedance 200k - - ? v rx-idle-det-diffp-p electrical idle detect threshold 65 - 175 mv t rx-idle-det- diffentertime unexpected electrical idle enter detect threshold integration time - - 10 ms l rx-skew total skew - - 20 ns note: refer to pci express base specification, rev.1.1, for correct measurement environment setting of each parameter. 8.8.3. refclk parameters table 26. refclk parameters symbol parameter 100mhz input min max units note rise edge rate rising edge rate 0.6 4.0 v/ns 2, 3 fall edge rate falling edge rate 0.6 4.0 v/ns 2, 3 v ih differential input high voltage +150 - mv 2 v il differential input low voltage - -150 mv 2 v cross absolute crossing point voltage +250 +550 mv 1, 4, 5 v cross delta variation of v cross over all rising clock edges - +140 mv 1, 4, 9 v rb ring-back voltage margin -100 +100 mv 2, 12 t stable time before v rb is allowed 500 - ps 2, 12 t period avg average clock period accuracy -300 +2800 ppm 2, 10, 13 t period abs absolute period (including jitter and spread spectrum) 9.847 10.203 ns 2, 6 t ccjitter cycle to cycle jitter - 150 ps 2 v max absolute maximum input voltage - +1.15 v 1, 7 v min absolute minimum input voltage - -0.3 v 1, 8
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 32 track id: jatr-2265-11 rev. 1.8 symbol parameter 100mhz input min max units note duty cycle duty cycle 40 60 % 2 rise-fall matching rising edge rate (refclk+) to falling edge rate (refclk-) matching - 20 % 1, 14 z c-dc clock source dc impedance 40 60 ? 1, 11 note1: measurement taken from single-ended waveform. note2: measurement taken from differential waveform. note3: measured from -150mv to + 150mv on the differential waveform (derived from re fclk+ minus refclk-). the signal must be monotonic through the measurement region for rise and fall time. the 300mv measurement window is centered on the differential zero crossing. see figure 20, page 34. note4: measured at crossing point wh ere the instantaneous voltage value of the rising edge of refclk+ equals the falling edge of refclk-. see figure 17, page 33. note5: refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. refers to all crossing points for this measurement. see figure 17, page 33. note6: defines as the absolute minimu m or maximum instantaneous period. this includes cycle to cycle jitter, relative ppm tolerance, and spread spectrum modulation. see figure 19, page 33. note7: defined as the maximum instantaneous voltage including overshoot. see figure 17, page 33. note8: defined as the minimum instantaneous voltage including undershoot. see figure 17, page 33. note9: defined as the total variation of all crossing volta ges of rising refclk+ and falling refclk-. this is the maximum allowed variance in vcross for any particular system. see figure 17, page 33. note10: refer to section 4.3.2.1 of the pci express base specification, revision 1.1 for information regarding ppm considerations. note11: system board compliance measurements must use the test load card described in figure 23, page 35. refclk+ and refclk- are to be measured at the load capacitors cl. single ended probes must be used for measurements requiring single ended measurements. either single ended probes with math or differential probe can be used for differential measurements. test load cl=2pf. note12: t stable is the time the differential clock must maintain a minimum 150mv differential voltage after rising/falling edges before it is allowed to droop back into the v rb 100mv differential range. see figure 22, page 34. note13: ppm refers to parts per million and is a dc absol ute period accuracy specification. 1ppm is 1/1,000,000 th of 100.000000mhz exactly, or 100hz. for 300ppm then we have an error budget of 100hz/ppm*300ppm=30khz. the period is to be measured with a frequency counter with measurement window set to 100ms or greater. the 300ppm applies to systems that do not employ spread spectrum or that use common clock source. for systems employing spread spectrum there is an additional 2500ppm nominal shift in maximum period resulting from the 0.5% down spread resulting in a maximum average period specification of +2800ppm. note14: matching applies to rising edge rate for refclk+ and falling edge rate for refclk-. it is measured using a 75mv window centered on the median cross point where refclk+ rising meets refclk- falling. the median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. the rise edge rate of refclk+ should be compared to the fall edge ra te of refclk-; the maximum allowed difference should not exceed 20% of the slowest edge ra te. see figure 18, page 33. note15: refer to pci express card electromechanical specification, rev.1.1, for correct measurement environment setting of each parameter.
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 33 track id: jatr-2265-11 rev. 1.8 figure 17. single-ended measurement points for absolute cross point and swing figure 18. single-ended measurement points for delta cross point figure 19. single-ended measurement points for rise and fall time matching
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 34 track id: jatr-2265-11 rev. 1.8 figure 20. differential measurement points for duty cycle and period figure 21. differential measurement points for rise and fall time figure 22. differential measurement points for ringback
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 35 track id: jatr-2265-11 rev. 1.8 figure 23. reference clock system measurement point and loading 8.8.4. auxiliary signal timing parameters table 27. auxiliary signal timing parameters symbol parameter min max units t pvperl power stable to perstb inactive 100 - ms t perst-clk refclk stable before perstb inactive 100 - s t perst perstb active time 100 - s t fail power level invalid to pwrgd inactive - 500 ns t wkrf lanwakeb rise ? fall time - 100 ns figure 24. auxiliary signal timing
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 36 track id: jatr-2265-11 rev. 1.8 9. mechanical dimensions 9.1. rtl8111d & rtl8111d-vb (64-pin qfn) note: the rtl8111d(-vb)?s exposed pad size is l/f 3
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 37 track id: jatr-2265-11 rev. 1.8 9.2. rtl8111dl & rtl8111dl-vb (48-pin lqfp) 9.3. mechanical dimensions notes (rtl8111dl/rtl8111dl-vb 48-pin) symbol dimension in inchs dimension in millimeters min nom max min nom max a - - 0.063 - - 1.60 a1 0.002 0.004 0.006 0.00 0.1 0.15 a2 0.053 0.055 0.057 1.30 1.40 1.45 b 0.007 0.009 0.011 0.15 0.22 0.27 d/e 0.354 bsc 9.00 bsc d1/e1 0.276 bsc 7.00 bsc e 0.020 bsc 0.50 bsc l 0.018 0.024 0.030 0.45 0.60 0.75 l1 0.039 ref 1.00 ref note 1: controlling dime nsion: millimeter (mm). note 2: reference document: jedec ms-026.
rtl8111d(l)/rtl8111d(l)-vb datasheet integrated gigabit ethernet controller for pci express 38 track id: jatr-2265-11 rev. 1.8 10. ordering information table 28. ordering information part number package status RTL8111D-GR 64-pin qfn ?green? pa ckage with au bonding production rtl8111dl-gr 48-pin lqfp ?green? package with au bonding production rtl8111d-vb-gr 64-pin qfn ?green? package w ith au bonding; version b silicon production rtl8111dl-vb-gr 48-pin lqfp ?g reen? package with au bonding; version b silicon production rtl8111dl-vb-cg 48-pin lqfp ?green? package with cu bonding; version b silicon production note: see page 3 and page 4 for package identification information. realtek semiconductor corp. headquarters no. 2, innovation road ii hsinchu science park, hsinchu 300, taiwan tel.: +886-3-578-0211. fax: +886-3-577-6047 www.realtek.com

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